1. Field of the Invention
The invention relates in general to the computer automated design, and more particularly, to synthesis of multiple different implementations of a design.
2. Description of the Related Art
Modern circuit design has evolved into a specialized field often referred to as electronic design automation in which computers and computer aided design (CAD) techniques are used to automate the integrated circuit (IC) design process. An IC design process typically begins with an engineer specifying the input/output signals, functionality and performance characteristics of a hardware circuit to be fabricated. These characteristics are captured in a high level hardware language model, which represents a design at a higher level of abstraction, which reduces the number of individual design objects that a designer needs to consider individually by perhaps orders of magnitude.
Synthesis can be defined broadly as a translation process from a behavioral description of a design to a structural description of the design, such as the design of an IC. A structural representation typically comprises a one-to-many mapping of a behavioral representation onto a set of components in accordance with design constraints such as cost, area, delay and power consumption. Each component in a structural design, in turn may be defined by its own behavioral description. Thus, a design can be represented behaviorally at many different levels of abstraction, and different software-based synthesis tools typically are used depending upon the level of abstraction at which a design is specified.
It is not unusual during design of device such as an integrated circuit, for a developer to try out or test several alternative design implementations. Implementation changes are communicated to a software-based synthesis tool as changes in one or more design constraints, for example. Accordingly different implementations may be represented as different lower level abstraction models synthesized from slightly different constraints upon the design. The different models then may be separately simulated to ascertain which one best satisfies overall design requirements, for example.
As such, it is common practice to run a synthesis tool a plurality of times on a design that is only marginally different from that of previous runs, as bugs are found in the original specifications or different choices are selected in the constraints, or perhaps both are changed.
In the past, synthesis tools typically began each synthesis run from scratch, considering the inputs as presented, without regard for previous decisions and calculations. An unfortunate problem with this prior approach is that even a small change in an input to the synthesis tool could result in a relatively large change in the output model produced by the tool when compared with a previously produced output model, as areas of behavior that were not constrained get mapped into equally valid, yet significantly different structures in the later output model. Differences between the earlier and later output models can result in significant difficulties for a designer, since any validation through verification of the earlier output model could be of little use, as the later output model could be different in many ways from the previously synthesized output model. As a consequence, as a practical matter, verification of the later output model often must start from the beginning with no benefit from prior verification results.
Thus, there has been a need for an improved approach to synthesis of different output model implementations during design of a device such as an IC. The present invention meets this need.